Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
An Algorithm for Optimal Logic Design Using Multiplexers
IEEE Transactions on Computers
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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Among the various CMOS logic families, PTL has been recognized as one of the potential alternatives to static CMOS for the synthesis of high performance and low power circuits, Moreover, as BDDs can be readily mapped to PTL circuits, use of BDDs has been synonymous with the synthesis of PTL circuits. Most of the reported works on PTL synthesis are based on the Reduced Ordered BDDs (ROBDDs). We have developed a novel heuristic-based technique for obtaining Reduced Unordered BDDs (RUBDDs), which leads to circuits of smaller size having lesser delay and smaller power consumption compared to the existing results. We propose the technology mapping using the popular LEAP-like cells, such that the PTL circuit synthesis flow has the same flavor as that of the standard cell-based static CMOS circuit synthesis. We have also developed models for the estimation of delay and power consumption of the synthesized PTL circuits and compared those with the static CMOS and other existing PTL-based circuit realizations.