An Algorithm for Optimal Logic Design Using Multiplexers
IEEE Transactions on Computers
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Amap: A technology mapper for selector-based field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Characterization of Unate Cascade Realizability Using Parameters
IEEE Transactions on Computers
Universal Logic Modules and Their Applications
IEEE Transactions on Computers
A Decomposition Chart Technique to Aid in Realizations with Multiplexers
IEEE Transactions on Computers
ULM Implicants for Minimization of Univers Logic Module Circuits
IEEE Transactions on Computers
A Numerical Expansion Technique and Its Application to Minimal Multiplexer Logic Circuits
IEEE Transactions on Computers
Synthesis of high performance low power PTL circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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The introduction of multiplexer based FPGAs has renewed interest in logic design using multiplexers. This paper presents an iterative approach for the synthesis of combinational circuits using a tree network of 2-to-1 multiplexers. A characterizing parameter of Boolean functions, known as Ratio Parameters, has been used in each iteration to reduce the search space. The obtained multiplexer network is then mapped onto the Actel ACT1 FPGA basic blocks. The performance of the proposed approach has been evaluated by comparing the results of 11 MCNC benchmark problems with the results of the existing technology mappers.