Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Don't cares in multi-level network optimization
Don't cares in multi-level network optimization
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast discrete function evaluation using decision diagrams
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Decomposition Techniques for Efficient ROBDD Construction
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Multilevel Factorization Technique for Pass Transistor Logic
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Multiple-Output Shared Transistor Logic (MOSTL)
Multiple-Output Shared Transistor Logic (MOSTL)
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On the design of self-checking functional units based on Shannon circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A novel high throughput reconfigurable FPGA architecture
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Buffer minimization in pass transistor logic
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Wave-steering one-hot encoded FSMs
Proceedings of the 37th Annual Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the generation of multiplexer circuits for pass transistor logic
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnect pipelining in a throughput-intensive FPGA architecture
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
On-the-fly layout generation for PTL macrocells
Proceedings of the conference on Design, automation and test in Europe
Low power optimization technique for BDD mapped circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Latency and latch count minimization in wave steered circuits
Proceedings of the 38th annual Design Automation Conference
Technology mapping for high-performance static CMOS and pass transistor logic designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ordered binary decision diagrams as knowledge-bases
Artificial Intelligence
Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Wave steering to integrate logic and physical syntheses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
IEEE Transactions on Computers
PITIA: an FPGA for throughput-intensive applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Combination of Lower Bounds in Exact BDD Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exact lower bound for the number of switches in series to implement a combinational logic cell
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Synthesis of high performance low power PTL circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast disjoint transistor networks from BDDs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A comparative study of CMOS gates with minimum transistor stacks
Proceedings of the 20th annual conference on Integrated circuits and systems design
Weighted A∗ search -- unifying view and application
Artificial Intelligence
FSM Encoding for BDD Representations
International Journal of Applied Mathematics and Computer Science
IEEE Transactions on Circuits and Systems II: Express Briefs
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. In this work, we motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multi-stage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. We show that the proposed approach allows us to make logic-level optimizations similar to the traditional multi- level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do not have any equivalent in the traditional approach. We also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that our technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of our knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.