Fast disjoint transistor networks from BDDs

Authors:
Leomar S. da Rosa Junior;Felipe S. Marques;Tiago M. G. Cardoso;Renato P. Ribas;Sachin S. Sapatnekar;André I. Reis
Affiliations:
Universidade Federal do Rio Grande do Sul, Brazil;Universidade Federal do Rio Grande do Sul, Brazil;Universidade Federal do Rio Grande do Sul, Brazil;Universidade Federal do Rio Grande do Sul, Brazil;University of Minnesota;Universidade Federal do Rio Grande do Sul, Brazil
Venue:
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Year:
2006

Citing 9
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Abstract

In this paper, we describe different ways to derive transistor networks from BDDs. The use of disjoint pull-up (composed of PMOS transistors) and pull-down (composed of NMOS transistors) planes allows simplifications that result in shorter pull-up and pull-down transistor stacks. The reduced length of transistor stacks leads to the fastest implementation among the six different strategies evaluated to generate transistor networks from BDDs. Delay and area results are presented showing the impact of the proposed strategy.