Precomputation-based sequential logic optimization for low power
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A bipartition-codec architecture to reduce power in pipelined circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Low power optimization technique for BDD mapped circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Introduction to Algorithms
Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A bipartition-codec architecture to reduce power in pipelined circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact lower bound for the number of switches in series to implement a combinational logic cell
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Fast disjoint transistor networks from BDDs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A comparative study of CMOS gates with minimum transistor stacks
Proceedings of the 20th annual conference on Integrated circuits and systems design
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power reduction in PTL circuits to that of BDD decomposition and solve the latter using the max-flow min-cut technique. We use transistor level power estimates to guide the BDD decomposition algorithm. We present the results obtained by running our algorithm on a set of MCNC benchmark circuits, and show on an average of 47% power reduction over these circuits; the comparison with the previously proposed low power pass transistor logic synthesis algorithms shows an average improvement of over 23% over the best previously published approach.