BDD decomposition for delay oriented pass transistor logic synthesis

Authors:
Rupesh S. Shelar;Sachin S. Sapatnekar
Affiliations:
Intel Corporation, Hillsboro, OR and Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN;Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the max-flow min-cut technique to bipartition the BDD optimally under a cost function that measures the delay and area of the decomposed implementations. Experimental results obtained by running our algorithm on the set of ISCAS'85 benchmarks show a 31% improvement in delay and a 30% improvement in area, on an average, as compared to static CMOS implementations for XOR intensive circuits, while in case of arithmetic logic unit and control circuits that are NAND intensive, improvements over static CMOS are small and inconsistent.