Subthreshold leakage modeling and estimation of general CMOS complex gates

Authors:
Paulo F. Butzen;André I. Reis;Chris H. Kim;Renato P. Ribas
Affiliations:
Instituto de Informática, UFRGS, Porto Alegre, Brazil;Nangate Inc., Menlo Park, CA;EECS, University of Minnesota, MN;Instituto de Informática, UFRGS, Porto Alegre, Brazil
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

A new subthreshold leakage model is proposed in order to improve the static power estimation in general CMOS complex gates. Series-parallel transistor arrangements with more than two logic depth, as well as non-seriesparallel off-switch networks are covered by such analytical modeling. The occurrence of on-switches in off-networks, also ignored by previous works, is considered in the proposed analysis. The model has been validated through electrical simulations, taking into account transistor sizing, operating temperature, supply voltage and threshold voltage variations.