Logic circuits operating in subthreshold voltages
Proceedings of the 2006 international symposium on Low power electronics and design
Modeling and estimating leakage current in series-parallel CMOS networks
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Leakage Minimization Technique for Nanoscale CMOS VLSI
IEEE Design & Test
VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Proceedings of the 18th ACM Great Lakes symposium on VLSI
On Composite Leakage Current Maximization
Journal of Electronic Testing: Theory and Applications
UDSM subthreshold leakage model for NMOS transistor stacks
Microelectronics Journal
Statistical timing and leakage power analysis of PD-SOI digital circuits
Analog Integrated Circuits and Signal Processing
Subthreshold leakage modeling and estimation of general CMOS complex gates
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and gate leakage power, is becoming more significant compared to dynamic power when technology scaling down below 100nm. Consequently, fast and accurate leakage power estimation models, which are strongly dependent on precise modeling of the stacking effect on subthreshold leakage and gate leakage, are vital for evaluating optimizations. In this work, making use of the interactions between subthreshold leakage and gate leakage, we focus our attention on analyzing the effects of transistor stacking on gate leakage between the channel and the gate and that between the drain/source and the gate. The contribution of the latter has been largely ignored in prior work, while our work shows that it is an important factor. Based on the stacking effect analysis, we have proposed a new best input vector to reduce the total leakage power; and an efficient and accurate leakage power estimation macro-model which achieves a mean error of 3.1% when compared to HSPICE.