Leakage Minimization Technique for Nanoscale CMOS VLSI

Authors:
Kyung Ki Kim;Yong-Bin Kim;Minsu Choi;Nohpill Park
Affiliations:
Northeastern University;Northeastern University;University of Missouri-Rolla;Oklahoma State University, Stillwater
Venue:
IEEE Design & Test
Year:
2007

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Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)

Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)

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Abstract

This article proposes a new heuristic approach to determine the input patterns that minimize leakage currents of nanometer CMOS circuits during sleep mode. The proposed approach uses a new macromodeling technique to characterize the minimum leakage current of each individual cell, considering fan-out effects, stack effect, and the interaction between gate-leakage and subthreshold currents. Experimental results shows that the methodology using the proposed macromodel provides less than a 4% error compared to Hspice simulation results.