Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing stand-by leakage power in static CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1,2
Proceedings of the 2002 international symposium on Low power electronics and design
Discrete Applied Mathematics
Implications of technology scaling on leakage reduction techniques
Proceedings of the 40th annual Design Automation Conference
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Enhanced leakage reduction Technique by gate replacement
Proceedings of the 42nd annual Design Automation Conference
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 43rd annual Design Automation Conference
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
Proceedings of the conference on Design, automation and test in Europe
Leakage Minimization Technique for Nanoscale CMOS VLSI
IEEE Design & Test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Leakage current optimization techniques during test based on don't care bits assignment
Journal of Computer Science and Technology
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
DFT and minimum leakage pattern generation for static power reduction during test and burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Controlling NBTI degradation during static burn-in testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
M-IVC: Applying multiple input vectors to co-optimize aging and leakage
Microelectronics Journal
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We present two approaches to leakage power minimization in static CMOS circuits by means of input vector control (IVC). We model leakage effects using pseudo-Boolean functions. These are incorporated into an optimal integer linear programming model called VG-ILP that analyzes leakage variation with respect to a circuit's input vectors. A heuristic mixed-integer linear programming (MLP) method is also presented which has several advantages: it is faster, its accuracy can be quickly estimated, and trade-offs between runtime and optimality can easily be made. The proposed methods are used to generate a large set of experimental results on leakage reduction. It is shown that average leakage currents are usually 1.25 times the minimum, confirming the effectiveness of IVC. The heuristic MLP approach is much faster than exact ILP, while finding input vectors whose power consumption is only a few percent from the optimum.