Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Exact and heuristic approaches to input vector control for leakage power reduction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A New Simulation Method for NBTI Analysis in SPICE Environment
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
Proceedings of the conference on Design, automation and test in Europe
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
Handbook of Algorithms for Physical Design Automation
Handbook of Algorithms for Physical Design Automation
Skew management of NBTI impacted gated clock trees
Proceedings of the 19th international symposium on Physical design
Analysis and optimization of NBTI induced clock skew in gated clock trees
Proceedings of the Conference on Design, Automation and Test in Europe
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Negative Bias Temperature Instability (NBTI) has emerged as the dominant PMOS device failure mechanism in the nanometer VLSI era. The extent of NBTI degradation of a PMOS device increases dramatically at elevated operating temperature and supply voltage. Unfortunately, both these conditions are concurrently experienced by a VLSI chip during the process of burn-in testing. Our analysis shows that even with a short burn-in duration of 10 hours, the degradation accumulated can be as much as 60% of the NBTI degradation experienced over 10 years of use at nominal conditions. Static burn-in testing in particular is observed to cause most NBTI degradation due to absence of relaxation phase unlike the case for dynamic burn-in testing. The delay of benchmark circuits is observed to increase by over 10% due to static burn-in testing. We propose the first technique to reduce the NBTI degradation during static burn-in test by finding the minimum NBTI induced delay degradation vector (MDDV) based on timing criticality and threshold voltage change (ΔVTH) sensitivity of the cells. Further, only a subset of the input pins need to be controlled for NBTI reduction, thus our technique allows other objectives (such as leakage reduction) to be considered simultaneously. Experimental results show that the NBTI induced critical path delay degradation can be reduced by more than 50% using our proposed technique.