A new polynomial-time algorithm for linear programming
Combinatorica
Proud: a fast sea-of-gates placement algorithm
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
APT: an area-performance-testability driven placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A fast physical constraint generator for timing driven layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Fuzzy logic approach to placement problem
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A performance driven macro-cell placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An adaptive timing-driven layout for high speed VLSI
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A new min-cut placement algorithm for timing assurance layout design meeting net length constraint
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance-driven constructive placement
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Dynamic prediction of critical paths and nets for constructive timing-driven placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing- and constraint-oriented placement for interconnected LSIs in mainframe design
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Experiments with a performance driven module generator
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
PERFLEX: a performance driven module generator
EURO-DAC '92 Proceedings of the conference on European design automation
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Compression-relaxation: a new approach to performance driven placement for regular architectures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Delay and area optimization for compact placement by gate resizing and relocation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A global router optimizing timing and area for high-speed bipolar LSI's
DAC '94 Proceedings of the 31st annual Design Automation Conference
A delay driven FPGA placement algorithm
EURO-DAC '94 Proceedings of the conference on European design automation
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A timing-driven data path layout synthesis with integer programming
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A performance-driven IC/MCM placement algorithm featuring explicit design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Relaxation and clustering in a local search framework: application to linear placement
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Analytical minimization of half-perimeter wirelength
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Net criticality revisited: an effective method to improve timing in physical design
Proceedings of the 2002 international symposium on Physical design
Wire length prediction in constraint driven placement
Proceedings of the 2003 international workshop on System-level interconnect prediction
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Effective Heuristics for Timing Driven Constructive Placement
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement
Journal of VLSI Signal Processing Systems
CNB: a critical-network-based timing optimization method for standard cell global routing
Journal of Computer Science and Technology
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
An approach to placement-coupled logic replication
Proceedings of the 41st annual Design Automation Conference
Optimality and Stability Study of Timing-Driven Placement Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Skew-programmable clock design for FPGA and skew-aware placement
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A study of tighter lower bounds in LP relaxation based placement
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An analytic placer for mixed-size placement and timing-driven placement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An LP-based methodology for improved timing-driven placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
New timing and routability driven placement algorithms for FPGA synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Criticality history guided FPGA placement algorithm for timing optimization
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Path smoothing via discrete optimization
Proceedings of the 45th annual Design Automation Conference
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
Controlling NBTI degradation during static burn-in testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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The increasingly important role of the interconnect in the timing performance of present and future integrated circuit technologies underscores the need to reconsider conventional physical design CAD tools, and devise new ways to influence performance during layout. Interconnects are not perfect conductors, they introduce parasitic elements that load the logic gates and distort the temporal properties of the design as viewed by the logic designer. Cell placement that minimizes wirelength as the sole objective does not solve the problem, leaving a margin for performance improvement that has not been fully exploited. This paper presents a novel approach to performance-driven placement, combining timing analysis and physical design to dynamically optimize the performance of the chip during placement. The ideas are embodied in a program named Allegro, and preliminary results tested on Sea-of-Gate designs are encouraging.