Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
APT: an area-performance-testability driven placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Delay and area optimization in standard-cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Algorithms for library-specific sizing of combinational logic
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
Gate sizing with controlled displacement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Using partitioning to help convergence in the standard-cell design automation methodology
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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In this paper, we first present an efficient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit layout. Since the gate sizing procedure is embedded within the placement adjustment process, interconnect capacitance information is included in the gate size selection process. As a result, the algorithm is able to obtain superior solutions.