Graph Theory in Modern Engineering: Computer Aided Design, Optimization, Reliability Analysis
Graph Theory in Modern Engineering: Computer Aided Design, Optimization, Reliability Analysis
A fast physical constraint generator for timing driven layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A performance driven macro-cell placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Dynamic prediction of critical paths and nets for constructive timing-driven placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing- and constraint-oriented placement for interconnected LSIs in mainframe design
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance oriented rectilinear Steiner trees
DAC '93 Proceedings of the 30th international Design Automation Conference
High-performance routing trees with identified critical sinks
DAC '93 Proceedings of the 30th international Design Automation Conference
Iterative wirability and performance improvement for FPGAs
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Delay and area optimization for compact placement by gate resizing and relocation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A global router optimizing timing and area for high-speed bipolar LSI's
DAC '94 Proceedings of the 31st annual Design Automation Conference
Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
Minimal delay interconnect design using alphabetic trees
DAC '94 Proceedings of the 31st annual Design Automation Conference
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Area-speed tradeoffs for hierarchical field-programmable gate arrays
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fast and accurate estimation of floorplans in logic/high-level synthesis
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Timing-driven placement for hierarchical programmable logic devices
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Proceedings of the 2003 international symposium on Physical design
Design topology aware physical metrics for placement analysis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Adaptive delay estimation for partitioning-driven PLD placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Automatic clock tree generation in ASIC designs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Effective Heuristics for Timing Driven Constructive Placement
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An Adaptive Interconnect-Length Driven Placer
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
Timing, energy, and thermal performance of three-dimensional integrated circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Individual wire-length prediction with application to timing-driven placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new LP based incremental timing driven placement for high performance designs
Proceedings of the 43rd annual Design Automation Conference
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The Timing Drive Placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during placement. TDP is significant because convergence to a timed wirable solution early in the physical design cycle is achieved, or else it becomes apparent that logic changes are required.