Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An adaptive timing-driven layout for high speed VLSI
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Experiments with a performance driven module generator
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-performance routing trees with identified critical sinks
DAC '93 Proceedings of the 30th international Design Automation Conference
Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Power distribution topology design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simultaneous gate and interconnect sizing for circuit-level delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Post routing performance optimization via tapered link insertion and wiresizing
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Post routing performance optimization via multi-link insertion and non-uniform wiresizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Delay bounded buffered tree construction for timing driven floorplanning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Routing tree topology construction to meet interconnect timing constraints
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A novel technique for sea of gates global routing
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
A performance-driven MCM router with special consideration of crosstalk reduction
Proceedings of the conference on Design, automation and test in Europe
Self-reforming routing for stochastic search in VLSI interconnection layout
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A construction of minimal delay Steiner tree using two-pole delay model
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Delay-related secondary objectives for rectilinear Steiner minimum trees
Discrete Applied Mathematics - The 1st cologne-twente workshop on graphs and combinatorial optimization (CTW 2001)
Elmor model-based algorithm to select optimal connections on the clock tree
Automation and Remote Control
Construction of rectilinear Steiner minimum trees with slew constraints over obstacles
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 2014 on International symposium on physical design
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