Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
Balancing minimum spanning and shortest path trees
SODA '93 Proceedings of the fourth annual ACM-SIAM Symposium on Discrete algorithms
IEEE Design & Test
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Delay Models for MCM Interconnects when Response is Non-Monotone
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Near-optimal critical sink routing tree constructions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire-sizing optimization with inductance consideration using transmission-line model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we will study the construction of a Steiner routing tree for a given net with the objective of minimizing the delay of the routing tree. Previous researches adopt Elmore delay model to compute delay. However, with the advancement of IC technology, a more accurate delay model is required. Therefore, in this paper, we will use two-pole delay model to compute the cost function of a Steiner tree. Moreover, we propose a new algorithm to construct the Steiner tree. Our algorithm takes into consideration the net topology, the total wire length and the longest path from the source to sink. Experimental results show that our algorithm is very effective and efficient as compared to [8].