Buffered Steiner trees for difficult instances
Proceedings of the 2001 international symposium on Physical design
A construction of minimal delay Steiner tree using two-pole delay model
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Congestion-driven codesign of power and signal networks
Proceedings of the 39th annual Design Automation Conference
Layer assignment for reliable system-on-package
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Simultaneous floorplanning and buffer block planning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Timing-driven Steiner trees are (practically) free
Proceedings of the 43rd annual Design Automation Conference
Maze routing steiner trees with effective critical sink optimization
Proceedings of the 2007 international symposium on Physical design
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A practical repeater insertion flow
Proceedings of the 18th ACM Great Lakes symposium on VLSI
On improving optimization effectiveness in interconnect-driven physical synthesis
Proceedings of the 2009 international symposium on Physical design
Proceedings of the 2009 international symposium on Physical design
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
Maze routing Steiner trees with delay versus wire length tradeoff
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Narrow-Shallow-Low-Light Trees with and without Steiner Points
SIAM Journal on Discrete Mathematics
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Analysis of Elmore delay in distributed RC tree structures shows the influence of both tree cost and tree radius on signal delay in VLSI interconnects. We give new and efficient interconnection tree constructions that smoothly combine the minimum cost and the minimum radius objectives, by combining respectively optimal algorithms due to Prim (1957) and Dijkstra (1959). Previous “shallow-light” techniques are both less direct and less effective: in practice, our methods achieve uniformly superior cost-radius tradeoffs. Timing simulations for a range of IC and MCM interconnect technologies show that our wirelength savings yield reduced signal delays when compared to shallow-light or standard minimum spanning tree and Steiner tree routing