A global router based on a multicommodity flow model
Integration, the VLSI Journal
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Simultaneous signal and power routing under K model
Proceedings of the 2001 international workshop on System-level interconnect prediction
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Area minimization of power distribution network using efficient nonlinear programming techniques
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
Analysis and Optimization of Power Grids
IEEE Design & Test
Full-Chip Multilevel Routing for Power and Signal Integrity
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic congestion model considering shielding for crosstalk reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Full-chip multilevel routing for power and signal integrity
Integration, the VLSI Journal
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2008 international symposium on Physical design
Priority-based routing resource assignment considering crosstalk
Journal of Computer Science and Technology
Extended global routing with RLC crosstalk constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient shield insertion for inductive noise reduction in nanometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
We present a global wire design methodology that simultaneously considers the performance needs for both signal lines and power grids under congestion considerations. An iterative procedure is employed in which the global routing is performed according to a congestion map that includes the resource utilization of the power grid, followed by a step in which the power grid is adjusted to relax the congestion in crowded regions. This adjustment is in the form of wire removal in noncritical regions, followed by a wire sizing step that overcomes the effects of wire removal. Experimental results show that the overall routability can be significantly improved while the power grid noise is maintained within the voltage droop constraint.