Automatic sizing of power/ground (P/G) networks in VLSI
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Optimum design of reliable IC power networks having general graph topologies
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Current signature compression for IR-drop analysis
Proceedings of the 37th Annual Design Automation Conference
Design of robust global power and ground networks
Proceedings of the 2001 international symposium on Physical design
Technology trends in power-grid-induced noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
Congestion-driven codesign of power and signal networks
Proceedings of the 39th annual Design Automation Conference
Area minimization of power distribution network using efficient nonlinear programming techniques
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Multigrid-like technique for power grid analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Full-Chip Multilevel Routing for Power and Signal Integrity
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Thermal and Power Integrity Based Power/Ground Networks Optimization
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A fast algorithm for power grid design
Proceedings of the 2005 international symposium on Physical design
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Gibbs sampling in power grid analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplan and power/ground network co-synthesis for fast design convergence
Proceedings of the 2006 international symposium on Physical design
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
On-chip decoupling capacitance and P/G wire co-optimization for dynamic noise
Proceedings of the 44th annual Design Automation Conference
Analysis and optimization of power-gated ICs with multiple power gating configurations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel technique for incremental analysis of on-chip power distribution networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimization of via distribution and stacked via in multi-layered P/G networks
Integration, the VLSI Journal
An efficient decoupling capacitance optimization using piecewise polynomial models
Proceedings of the Conference on Design, Automation and Test in Europe
On-chip power network optimization with decoupling capacitors and controlled-ESRs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Reliability analysis and optimization of power-gated ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated circuit security techniques using variable supply voltage
Proceedings of the 48th Design Automation Conference
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In this paper, we present a novel multigrid-based technique for on-chip power supply network optimization. We reduce a large-scale network to a much coarser one which can be efficiently optimized. The solution for the original network is then quickly computed using a back-mapping process. We model the power grid by an RLC network and use time-varying current sources to capture the on-chip switching. Our technique is capable of optimizing power grid and decoupling capacitance simultaneously. Experimental results show that the proposed technique provides more robust and area-efficient solutions than those obtained by the earlier approaches. It also provides a significant speed-up and brings up a possibility of incorporating power supply network optimization into other physical design stages such as signal routing.