Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
Power grid reduction based on algebraic multigrid principles
Proceedings of the 40th annual Design Automation Conference
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
Design and Analysis of Power Distribution Networks with Accurate RLC Models
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power grid plays an important role in determining circuit performance, and the accuracy and efficiency of power grid analysis algorithm has become critical in timing, power and noise estimation of modern integrated circuits. In this paper a stochastic algorithm based on Gibbs sampling is proposed to solve the problem of power grid analysis, and the test results shows that it reaches a good accuracy with linear complexity. The method has incremental property of localizing computation, a desirable property favoring in modern CAD. Therefore it can be embedded at all the design and verification levels of integrated circuits.