Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
Power network analysis using an adaptive algebraic multigrid approach
Proceedings of the 40th annual Design Automation Conference
Analysis and Optimization of Power Grids
IEEE Design & Test
Early-stage power grid analysis for uncertain working modes
Proceedings of the 2004 international symposium on Physical design
Optimal placement of power supply pads and pins
Proceedings of the 41st annual Design Automation Conference
A stochastic approach To power grid analysis
Proceedings of the 41st annual Design Automation Conference
Vectorless Analysis of Supply Noise Induced Delay Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Hierarchical random-walk algorithms for power grid analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Two-Level Power-Grid Model for Transient Current Testing Evaluation
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 42nd annual Design Automation Conference
A chip-level electrostatic discharge simulation strategy
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
HiSIM: hierarchical interconnect-centric circuit simulator
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Floorplanning with power supply noise avoidance
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Gibbs sampling in power grid analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Relaxed hierarchical power/ground grid analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 international symposium on Physical design
High accurate pattern based precondition method for extremely large power/ground grid analysis
Proceedings of the 2006 international symposium on Physical design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fast algorithms for IR drop analysis in large power grid
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Large power grid analysis using domain decomposition
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Accurate power grid analysis with behavioral transistor network modeling
Proceedings of the 2007 international symposium on Physical design
On-chip decoupling capacitance and P/G wire co-optimization for dynamic noise
Proceedings of the 44th annual Design Automation Conference
Large scale P/G grid transient simulation using hierarchical relaxed approach
Integration, the VLSI Journal
Parallel domain decomposition for simulation of large-scale power grids
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel technique for incremental analysis of on-chip power distribution networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks
Integration, the VLSI Journal
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Context-sensitive static transistor-level IR analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Electromigration study of power-gated grids
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
GPU friendly fast Poisson solver for structured power grid network analysis
Proceedings of the 46th Annual Design Automation Conference
Locality-driven parallel power grid optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Methodology for efficient substrate noise analysis in large-scale mixed-signal circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scaling power/ground solvers on multi-core with memory bandwidth awareness
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A parallel direct solver for the simulation of large-scale power/ground networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fast approximation technique for power grid analysis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
More realistic power grid verification based on hierarchical current and power constraints
Proceedings of the 2011 international symposium on Physical design
Locality-Driven Parallel Static Analysis for Power Delivery Networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel and scalable transient simulator for power grids via waveform relaxation (PTS-PWR)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient incremental analysis of on-chip power grid via sparse approximation
Proceedings of the 48th Design Automation Conference
Fast static analysis of power grids: algorithms and implementations
Proceedings of the International Conference on Computer-Aided Design
Vectorless verification of RLC power grids with transient current constraints
Proceedings of the International Conference on Computer-Aided Design
A hierarchical matrix inversion algorithm for vectorless power grid verification
Proceedings of the International Conference on Computer-Aided Design
Power supply selective mapping for accurate timing analysis
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
Deterministic random walk preconditioning for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Parallel forward and back substitution for efficient power grid simulation
Proceedings of the International Conference on Computer-Aided Design
Voltage propagation method for 3-D power grid analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Incremental transient simulation of power grid
Proceedings of the 2014 on International symposium on physical design
Scalable power grid transient analysis via MOR-assisted time-domain simulations
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.03 |
Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size