A chip-level electrostatic discharge simulation strategy

Authors:
Haifeng Qian;J. N. Kozhaya;S. R. Nassif;S. S. Sapatnekar
Affiliations:
Minnesota Univ., Minneapolis, MN, USA;Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA;Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA;Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

Citing 4
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Chip-level charged-device modeling and simulation in CMOS integrated circuits

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Abstract

This work presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node V/sub DD/ net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.