Locality-driven parallel power grid optimization

Authors:
Zhiyu Zeng;Peng Li
Affiliations:
Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX;Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

Citing 16
Cited 3

Automatic sizing of power/ground (P/G) networks in VLSI

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Power supply noise analysis methodology for deep-submicron VLSI chip design

DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast power grid simulation

Proceedings of the 37th Annual Design Automation Conference
Random walks in a supply network

Proceedings of the 40th annual Design Automation Conference
Power grid reduction based on algebraic multigrid principles

Proceedings of the 40th annual Design Automation Conference
On the implementation of an interior-point filter line-search algorithm for large-scale nonlinear programming

Mathematical Programming: Series A and B
Fast flip-chip power grid analysis via locality and grid shells

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Large-scale nonlinear optimization in circuit tuning

Future Generation Computer Systems
Thousand core chips: a technology perspective

Proceedings of the 44th annual Design Automation Conference
A geometric approach for early power grid verification using current constraints

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Hierarchical analysis of power distribution networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multigrid-like technique for power grid analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Area minimization of power distribution network using efficient nonlinear programming techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip power-supply network optimization using multigrid-based technique

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partition-based algorithm for power grid design using locality

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Multicore parallelization of min-cost flow for CAD applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Fast algorithms for IR voltage drop analysis exploiting locality

Proceedings of the 48th Design Automation Conference
Efficient algorithms for fast IR drop analysis exploiting locality

Integration, the VLSI Journal

Quantified Score

Hi-index	0.03

Visualization

Abstract

Large very large-scale-integration power/ground distribution networks are challenging to analyze and design due to the sheer network complexity. In this paper, a parallel sizing optimization approach is presented to minimize the wiring area of a power grid while meeting IR drop and electromigration constraints. Motivated by a proposed two-level hierarchical optimization, we present a novel locality-driven partitioning scheme to allow for divide-and-conquer-based scalable optimization of large power grids, which is infeasible via flat optimization. Unlike existing partitioning-based strategies, the proposed method is very flexible in terms of choice of partitioning boundaries and sizes. Equally importantly, it allows for simultaneous sizing of multiple partitions, leading itself naturally to parallelization.