Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings

Authors:
S. X.D. Tan;C. J.R. Shi;Jyh-Chwen Lee
Affiliations:
Dept. of Electr. Eng., California Univ., Riverside, CA, USA;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

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Abstract

This paper presents a new method of sizing the widths of the power and ground routes in integrated circuits so that the chip area required by the routes is minimized subject to electromigration and IR voltage drop constraints. The basic idea is to transform the underlying constrained nonlinear programming problem into a sequence of linear programs. Theoretically, we show (that the sequence of linear programs always converges to the optimum solution of the relaxed convex optimization problem. Experimental results demonstrate that the proposed sequence-of-linear-program method Is orders of magnitude faster than the best-known method based on conjugate gradients with constantly better solution qualities.