Analog Integrated Circuits and Signal Processing
Simultaneous switching noise in on-chip CMOS power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Scaling trends of on-chip power distribution noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
Inductance model of interdigitated power and ground distribution networks
IEEE Transactions on Circuits and Systems II: Express Briefs
Inductive properties of high-performance power distribution grids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip power-supply network optimization using multigrid-based technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partition-based algorithm for power grid design using locality
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Higher operating frequencies and greater power demands have increased the requirements on the power and ground network. Simultaneously, due to the larger current loads, current densities are increasing, making electromigration an important design issue. In this paper, methods for optimizing a multi-layer interdigitated power and ground network are presented. Based on the resistive and inductive (both self- and mutual) impedance, a closed-form solution for determining the optimal power and ground wire width is described, producing the minimum impedance for a single metal layer. Electromigration is considered, permitting the appropriate number of metal layers to be determined. The tradeoff between the network impedance and current density is investigated. Based on 65-, 45-, and 32-nm CMOS technologies, the optimal width as a function of metal layer is determined for different frequencies, suggesting important trends for interdigitated power and ground networks.