Thermal and Power Integrity Based Power/Ground Networks Optimization
Proceedings of the conference on Design, automation and test in Europe - Volume 2
P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On-chip bus thermal analysis and optimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-line sensing for healthier FPGA systems
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Line width optimization for interdigitated power/ground networks
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Emulating and diagnosing IR-drop by using dynamic SDF
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Multi-layer interdigitated power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of the conditions for the worst case switching activity in integrated circuits
Analog Integrated Circuits and Signal Processing
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power supply selective mapping for accurate timing analysis
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
IR-drop reduction through combinational circuit partitioning
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
| Hi-index | 0.00 |
This paper presents a detailed analysis of the power-supplyvoltage (IR) drop scaling in DSM technologies. For the first time, the effectsof temperature, electromigration and interconnect technology scaling(including resistivity increase of Cu interconnects due to electron surfacescattering and finite barrier thickness) are taken into consideration duringthis analysis. It is shown that the IR-drop effect in the power/ground (P/G)network increases rapidly with technology scaling, and using well-knowncounter measures such as wire-sizing and decoupling capacitor insertionwith resource allocation schemes that are typically used in the presentdesigns may not be sufficient to limit the voltage fluctuations over the powergrid for future technologies. It is also shown that such voltage drops onpower lines of switching devices in a clock network can introducesignificant amount of skew which in turn degrades the signal integrity.