Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An exact solution to the minimum size test pattern problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generic ILP versus specialized 0-1 ILP: an update
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Generating Realistic Stimuli for Accurate Power Grid Analysis
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Estimation of average switching activity in combinational logic circuits using symbolic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Relentless advances in IC technologies have fueled steady increases on fabricated component density and working frequencies. As feature sizes decrease to nanometer scales, an increase in switching activity per unit of area and time is observed. When extreme switching activity occurs in a small region of an integrated circuit, malfunctions may be triggered that compromise behavior. This can be either a consequence of a decrease in bias levels in the power grid caused by IR-Drop, or due to unexpected glitching on gates' outputs caused by ground bounce. For proper circuit verification, both conditions have to be accurately estimated and accounted for. Achieving this in an accurate manner for a large circuit is a very challenging problem. In this paper we propose and compare methods for the identification of the conditions leading to extreme situations of switching activity in integrated circuits. Our approach is based on both spatial and time partitioning which are used to address the accuracy and computational requirements. We propose a method for determining the exact conditions for worst case switching activity in a small circuit area during a short time interval. We then show how this method can be combined with partitioning to allow for accurate full circuit verification.