Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Process-Aggravated Noise (PAN): New Validation and Test Problems
Proceedings of the IEEE International Test Conference on Test and Design Validity
Modeling the Effect of Ground Bounce on Noise Margin
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Estimation of maximum power supply noise for deep sub-micron designs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Frequency domain analysis of switching noise on power supply network
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ramp Up/Down Functional Unit to Reduce Step Power
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
5.1 Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Generation for Ground Bounce in Internal Logic Circuitry
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Instruction Prediction for Step Power Reduction
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Dynamic Timing Analysis Considering Power Supply Noise Effects
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Experimental measurement of a novel power gating structure with intermediate power saving mode
Proceedings of the 2004 international symposium on Low power electronics and design
Analysis of the impact of bus implemented EDCs on on-chip SSN
Proceedings of the conference on Design, automation and test in Europe: Proceedings
VLIW instruction scheduling for minimal power variation
ACM Transactions on Architecture and Code Optimization (TACO)
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Enhanced leakage reduction techniques using intermediate strength power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Reducing peak power with a table-driven adaptive processor core
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis of the conditions for the worst case switching activity in integrated circuits
Analog Integrated Circuits and Signal Processing
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Ground bounce occurs in integrated circuits and can cause signal distortion and increase gate delay. This can result in improper circuit operation. In the past, the switching of input/output buffers was the primary cause of the ground bounce. In designs employing deep sub-micron technology, high operating frequency, and short rise/fall times, ground bounce due to switching in internal circuitry becomes a potential problem. In this paper experiments based on realistic assumptions are performed to explore the properties of ground bounce. Experiments indicate that (1) ground bounce is generated in gates, irrespective of whether outputs switch from 0 to 1 or from 1 to 0, (2) ground bounce is reduced when the load capacitance increases, and (3) ground bounce decreases when the number of gates that switch is held constant while the number of gates that don't switch increases. These conclusions are different from what has been found when input/output buffers switch and lead to new design, verification and test issues.