Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Optimal Interconnect ATPG Under a Ground-Bounce Constraint
Journal of Electronic Testing: Theory and Applications
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The problem of generating DC parametric test patterns while reducing ground bounce is considered. A clear tradeoff is identified between test time and the amount ground bounce. An algorithm generating input DC tests with minimum ground bounce is proposed. Furthermore, we propose algorithms for reducing ground bounce for output DC tests under test time constraints based on the amount of information available. Experimental results prove that these algorithms not only reduce ground bounce but also keep test time within reasonable limits.