5.1 Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Handbook of Mathematical Functions, With Formulas, Graphs, and Mathematical Tables,
Handbook of Mathematical Functions, With Formulas, Graphs, and Mathematical Tables,
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In order to prevent ground bounce, Automatic Test Pattern Generation (ATPG) algorithms for wire interconnects have recently been extended with the capability to restrict the maximal Hamming distance between any two consecutive test patterns to a user-defined integer, referred to as the Simultaneously-Switching Outputs Limit (SSOL). The conventional approach to meet this SSOL constraint is to insert additional test patterns between consecutive test patterns if their Hamming distance is too large; this approach often leads to substantially more test patterns than strictly necessary. This paper presents an algorithm that generates, for a user-defined number of interconnect wires, a minimal set of test patterns that respects a user-defined SSOL constraint. Experimental results show that, in comparison to the conventional approach, our algorithm leads to a significant reduction of up to 60% in the test pattern count and corresponding test application time.