Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint

  • Authors:
  • Erik Jan Marinissen;Bart Vermeulen;Henk Hollmann;R. G. (Ben) Bennetts

  • Affiliations:
  • -;-;-;-

  • Venue:
  • IEEE Design & Test
  • Year:
  • 2003

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Abstract

Editor's note:When testing the interconnect structures on a board, test programmers sometimes ask, How can I control the test pattern generation process to avoid ground bounce problems during Extest mode? Those wishing to satisfy a simultaneously-switching-outputs constraint will find several new solutions in this article.ýMonica Lobetti-BodoniSiemens Mobile Communications