A minimized test pattern generation method for ground bounce effect and delay fault detection

Authors:
MoonJoon Kim;JeongMin Lee;WonGi Hong;Hoon Chang
Affiliations:
Department of Computing, Graduate School, Soongsil University, Seoul, Korea;Department of Computing, Graduate School, Soongsil University, Seoul, Korea;Department of Computing, Graduate School, Soongsil University, Seoul, Korea;School of Computing, Soongsil University, Seoul, Korea
Venue:
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV
Year:
2006

Citing 3
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Abstract

An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay faults detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.