A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500 (Frontiers in Electronic Testing)
Communication-Centric SoC Debug Using Transactions
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
3D Integration: Technology and Applications
3D Integration: Technology and Applications
IEEE Std 1500 Enables Modular SoC Testing
IEEE Design & Test
Testing Circuit-Partitioned 3D IC Designs
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Test Challenges for 3D Integrated Circuits
IEEE Design & Test
Proceedings of the 2009 International Conference on Computer-Aided Design
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
SOC test architecture and method for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Test Cost Analysis for 3D Die-to-Wafer Stacking
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
DfT Architecture for 3D-SICs with Multiple Towers
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1149.1 or IEEE Std 1500. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.