Low-power clock distribution in a multilayer core 3d microprocessor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From 3D circuit technologies and data structures to interconnect prediction
Proceedings of the 11th international workshop on System level interconnect prediction
Emerging technologies and their impact on system design
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips
Proceedings of the 46th Annual Design Automation Conference
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 2009 International Conference on Computer-Aided Design
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
The impact of liquid cooling on 3D multi-core processors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Interstratum connection design considerations for cost-effective 3-D system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost-aware three-dimensional (3D) many-core multiprocessor design
Proceedings of the 47th Design Automation Conference
Workload and network-optimized computing systems
IBM Journal of Research and Development
Guest Editorial: Current Trends in Low-Power Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Hardware trust implications of 3-D integration
WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Fabrication cost analysis and cost-aware design space exploration for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical circuit-switched NoC for multicore video processing
Microprocessors & Microsystems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning
Proceedings of the International Conference on Computer-Aided Design
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Journal of Electronic Testing: Theory and Applications
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
Journal of Electronic Testing: Theory and Applications
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
Journal of Electronic Testing: Theory and Applications
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Proceedings of the 2013 ACM international symposium on International symposium on physical design
An asymmetric adaptive-precision energy-efficient 3DIC multiplier
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Thermomechanical stress-aware management for 3D IC designs
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cell transformations and physical design techniques for 3D monolithic integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Asymmetric scaling on network packet processors in the dark silicon era
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
Compact lateral thermal resistance modeling and characterization for TSV and TSV array
Proceedings of the International Conference on Computer-Aided Design
Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os
Proceedings of the International Conference on Computer-Aided Design
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Three-dimensional die-stacking integration stacks multiple layers of processed silicon with a very high-density, low-latency layer-to-layer interconnect. After presenting a brief background on 3D die-stacking technology, this article gives multiple case studies on different approaches for implementing single-core and multicore 3D processors and discusses how to design future microprocessors given this emerging technology.