Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
The design of a low power asynchronous multiplier
Proceedings of the 2004 international symposium on Low power electronics and design
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Computer Architecture, Fifth Edition: A Quantitative Approach
Computer Architecture, Fifth Edition: A Quantitative Approach
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Decades of research in optimizing multipliers for power, speed, and area efficiency, and the continuing push for further enhancing multipliers reflects their importance. Energy-efficient computing requires optimization of every single logic component and hence, an energy-efficient 64-bit multiplier is proposed. This design exploits the highly frequent occurrence of low-precision operands, by dynamically adapting to asymmetric precision to save energy. Depending on input operands, it functions in three modes: 32x32, 64x64, or asymmetric 32x64/64x32. Results show that the asymmetric multiplier uses up to 42.4% less switching energy, and is overall up to 33.4% more energy-efficient than the baseline design. A 3-dimensional integrated circuit (3DIC) version of the asymmetric multiplier is also introduced. It is designed using a "design for 3D" methodology to mitigate some of the challenges of 3DIC. The average interconnect length and chip footprint of the 3DIC are 17.3% and 46.5% smaller than the traditional IC implementation.