Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing energy dissipation in high-speed multipliers
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low Power Digital CMOS Design
Power Management in the Amulet Microprocessors
IEEE Design & Test
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Precision selection for energy-efficient pixel shaders
Proceedings of the ACM SIGGRAPH Symposium on High Performance Graphics
An asymmetric adaptive-precision energy-efficient 3DIC multiplier
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low power multipliers: most inputs are positive, and most inputs have a small number of significant bits. These characteristics are exploited in the design of a multiplier that employs three techniques to minimize power consumption: asynchronous control, a radix-2 algorithm, and split registers. The power savings resulting from the use of these techniques are 55%, 23% and 12% respectively when compared to a synchronous multiplier using a radix-4 modified Booth's algorithm with unified registers. The results are derived from HSPICE simulations using input vectors from benchmark programs. A high-level software model is also used to compare the numbers of transitions in the various models.