Power Management in the Amulet Microprocessors

  • Authors:
  • Steve B. Furber;Aristides Efthymiou;Jim D. Garside;David W. Lloyd;Mike J. G. Lewis;Steve Temple

  • Affiliations:
  • -;-;-;-;-;-

  • Venue:
  • IEEE Design & Test
  • Year:
  • 2001

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Abstract

Amulet microprocessors are asynchronous (clockless) implementations of the ARM 32-bit RISC architecture. Their asynchronous control framework has positive benefits for low-power applications because it reduces activity to the minimum required to perform a task, whereas a clock inevitably incurs wasteful activity.