Communications of the ACM
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Cache and memory hierarchy design: a performance-directed approach
Cache and memory hierarchy design: a performance-directed approach
IBM Power and PowerPC
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI RISC Architecture and Organization
VLSI RISC Architecture and Organization
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power Management in the Amulet Microprocessors
IEEE Design & Test
Verification of Bounded Delay Asynchronous Circuits with Timed Traces
AMAST '98 Proceedings of the 7th International Conference on Algebraic Methodology and Software Technology
A way-halting cache for low-energy high-performance systems
ACM Transactions on Architecture and Code Optimization (TACO)
Integrated Computer-Aided Engineering
Architectural optimization for low-power nonpipelined asynchronous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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AMULET2e is an asynchronous microprocessor system based on the AMULET2 processor core. In addition to the processor it incorporates a number of distinct subsystems, the most notable of which is an asynchronous on-chip cache. This includes several novel features which exploit the asynchronous design style to increase throughput and reduce power consumption. These features are evident at a number of levels in the design. For example, the cache is micropipelined to increase its throughput, at the architectural level there is an arbitration free non-blocking line fetch mechanism while at the circuit design level there is a power-saving RAM sense amplifier control circuit. A significant property of the cache system is its ability to cycle in a data dependent way which allows the system to approach average case performance.