Communications of the ACM
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing verification for asynchronous design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
ARM System Architecture
Register Locking in an Asynchronous Microprocessor
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
The Design and Evaluation of an Asynchronous Microprocessor
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Scan testing of asynchronous sequential circuits
GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Scan testing of micropipelines
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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Asynchronous control offers potential advantages for embedded sys- tems due to its inherent power-efficiency, electromagnetic compatibility and modularity. However, the current design community isaverse to asynchronous design because it is perceived as being hard to design and manufacture. Recent developments in asynchronous design have begun to address these misconcep- tions and commercial interest is beginning to grow, but there are still few large-scale demonstrations of the practical application of asynchronous techniques to commercially interesting designs. This paper describes one such demonstrator. AMULET2e is an embedded system chip which incorporates a 32-bit RISC microprocessor, a cache memory and a exible memory interface, all of which operate asynchronously. This paper presents the motivation for asynchronous design, details of the AMULET2e organisation, the tools used to develop the design and the characteristics of the chip itself.