IEEE Transactions on Computers
Power Reduction in Custom CMOS Digital Filter Structures
Analog Integrated Circuits and Signal Processing - Special issue on selected papers from the 1997 NORCHIP conference
Fast Converter for 3 Moduli RNS Using New Property of CRT
IEEE Transactions on Computers
On the Design of IEEE Compliant Floating Point Units
IEEE Transactions on Computers
Improved merging of datapath operators using information content and required precision analysis
Proceedings of the 38th annual Design Automation Conference
IEEE Transactions on Parallel and Distributed Systems
Multilevel Reverse-Carry Addition: Single and Dual Adders
Journal of VLSI Signal Processing Systems
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
FPGA Adders: Performance Evaluation and Optimal Design
IEEE Design & Test
Integration, the VLSI Journal
Bit-level two's complement matrix multiplication
Integration, the VLSI Journal
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Dynamic Constant Coefficient Convolvers Implemented in FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Implementation of Multipliers in FPGA Structures
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
ITCC '00 Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00)
Evolutionary Synthesis of Arithmetic Circuit Structures
Artificial Intelligence Review
The design of a low power asynchronous multiplier
Proceedings of the 2004 international symposium on Low power electronics and design
Adding Limited Reconfigurability to Superscalar Processors
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
High-Speed Function Approximation Using a Minimax Quadratic Interpolator
IEEE Transactions on Computers
Highly efficient, limited range multipliers for LUT-based FPGA architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An architecture for elliptic curve cryptograph computation
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
Encyclopedia of Computer Science
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Evolutionary synthesis of arithmetic circuit structures
Artificial intelligence in logic design
Towards the automatic exploration of arithmetic-circuit architectures
Proceedings of the 43rd annual Design Automation Conference
Progressive decomposition: a heuristic to structure arithmetic circuits
Proceedings of the 44th annual Design Automation Conference
The Negative Two's Complement Number System
Journal of VLSI Signal Processing Systems
A binary floating-point adder with the signed-digit number arithmetic
CEA'07 Proceedings of the 2007 annual Conference on International Conference on Computer Engineering and Applications
Low-error, High-speed Approximation of the Sigmoid Function for Large FPGA Implementations
Journal of Signal Processing Systems
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Extended sequential logic for synchronous circuit optimization and its applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new VLSI architecture of parallel multiplier-accumulator based on radix-2 modified booth algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A FPGA version of a non-linear adaptive filter
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
PPAM'09 Proceedings of the 8th international conference on Parallel processing and applied mathematics: Part I
Signed multiplication technique by means of unsigned multiply instruction
Computers and Electrical Engineering
Implementations of square-root and exponential functions for large FPGAs
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Hardware implementation of the orbital function for quantum chemistry calculations
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
RAPANUI: rapid prototyping for media processor architecture exploration
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
CORDIC designs for fixed angle of rotation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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