Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation
IEEE Transactions on Computers
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Fault-secure shifter design: results and implementations
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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In this paper, several self-checking carry-propagate adders are examined and compared in terms of area integration, power dissipation and performance. Real-time detection of any single fault, permanent or transient, is ensured for all the presented circuits while the characteristics of each adder are illustrated. The results indicate that the characteristics of the adders change when safety mechanisms are applied. The constraints, also, of the required system design dictate the appropriate adder.