Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
Oscillation control in logic simulation using dynamic dominance graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal Self-Testing Embedded Parity Checkers
IEEE Transactions on Computers
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
A CAD framework for generating self-checking multipliers based on residue codes
DATE '99 Proceedings of the conference on Design, automation and test in Europe
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes
Journal of Electronic Testing: Theory and Applications
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Embedded self-testing checkers for low-cost arithmetic codes
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
IEEE Transactions on Computers
Self-Testing Embedded Borden t-UED Code Checkers for t=2kq-1 with q=2m-1
Journal of Electronic Testing: Theory and Applications
A fault-tolerant permutation network modulo arithmetic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.99 |
A method is proposed that is based on the partitioning of the input code variables into two sections, each section representing the binary form of a number Z/sub 1/ and Z/sub 2/, respectively. For a code with check base A=2/sup m/-1, two m-bit end-around carry adder trees calculate the modulo m residue of Z/sub 1/ and Z/sub 2/, while a totally self-checking (TSC) translator maps the output of the pair of trees onto m-variable two-rail code. A TSC two-rail checker maps the m-variable two-rail code onto one-out-of-two code. The checkers present significant improvement in the implementation cost, number of gate levels, and reliability over TSC checkers previously proposed in the literature.