A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
Design and performance of the IBM Enterprise System/900 Type 9121 Vector Facility
IBM Journal of Research and Development
On the effectiveness of residue code checking for parallel two's complement multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
Optimal Self-Testing Embedded Parity Checkers
IEEE Transactions on Computers
Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
Embedded Totally Self-Checking Checkers: A Practical Design
IEEE Design & Test
Guest Editors' Introduction: Online VLSI Testing
IEEE Design & Test
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
IEEE Transactions on Computers
Self-Checking Comparator with One Periodic Output
IEEE Transactions on Computers
Embedded self-testing checkers for low-cost arithmetic codes
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Design of Embedded Self-Testing Checkers for t-UED and BUED Codes
Journal of Electronic Testing: Theory and Applications
Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes"
Journal of Electronic Testing: Theory and Applications
Self-Testing Embedded Borden t-UED Code Checkers for t=2kq-1 with q=2m-1
Journal of Electronic Testing: Theory and Applications
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Code checkers that monitor the outputs of a system can detect both permanent and transient faults. We present two novel architectures of embedded self-testing checkers for low-cost and cyclic arithmetic codes, one based on code word generators and adders, the other based on code word accumulators. In these schemes, the code checker receives all possible code words but one, irrespective of the number of different code words that are produced by the circuit under check (CUC). So any code checker can be employed that is self-testing for all or a particular subset of code words, and the structure of the code checker need not be tailored to the set of code words produced by the CUC. The proposed code word generators and accumulators are built from simple standard hardware structures, counters and end-around-carry adders. They can also be utilized in an off-line BIST environment as pattern generators and test response compactors.