BIST Pattern Generators Using Addition and Subtraction Operations
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
An Accumulator-Based BIST Approach for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes
Journal of Electronic Testing: Theory and Applications
A novel reseeding technique for accumulator-based test pattern generation
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Effective Built-In Self-Test for Booth Multipliers
IEEE Design & Test
Embedded self-testing checkers for low-cost arithmetic codes
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Tailoring ATPG for Embedded Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On Accumulator-Based Bit-Serial Test Response Compaction Schemes
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Matrix-based software test data decompression for systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Configurations of registers and adders, subtracters, or arithmetic logic units, which are available in many data paths, can be utilized to generate test patterns and compact test responses. This paper analyzes aliasing in these configurations when the test responses of circuits with arbitrary combinational faults are compacted, and gives the limiting values that the aliasing probability tends to for increasing test lengths. Configurations that feed back the overflow during addition or the underflow during subtraction are the best choices. In some of them the probability of aliasing tends to a limiting value of 1/(2/sup k/-1), which is almost the same as in compactors based on linear feedback shift registers with irreducible characteristic polynomials.