An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Design of a C-testable booth multiplier using a realistic fault model
Journal of Electronic Testing: Theory and Applications
C-testable modified-Booth multipliers
Journal of Electronic Testing: Theory and Applications
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
An Effective BIST Scheme for Ring-Address Type FIFOs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An effective BIST architecture for fast multiplier cores
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Deterministic software-based self-testing of embedded processor cores
Proceedings of the conference on Design, automation and test in Europe
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Journal of Electronic Testing: Theory and Applications
Power-/Energy Efficient BIST Schemes for Processor Data Paths
IEEE Design & Test
Easily Testable Cellular Carry Lookahead Adders
Journal of Electronic Testing: Theory and Applications
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Design-for-testability techniques for CORDIC design
Microelectronics Journal
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Module generators provided by library vendors supply chip designers with optimized Booth multipliers which are widely used, as embedded cores, in both general purpose datapath structures and specialized Digital Signal Processors. Testing of such multipliers deeply embedded in complex ICs requires the utilization of an effective BIST scheme that can be easily synthesized along with the multiplier by the module generator. The BIST scheme for Booth multipliers, introduced in this paper, completely complies with this requirement. The algorithmic BIST patterns that this scheme generates guarantee a fault coverage higher than 99%. The required Test Pattern Generator consists of a simple fixed-size either binary counter or maximum length LFSR, independent of the size of the multiplier. Accumulator-based compaction is adopted since multipliers and adders co-exist in datapath structures. A new accumulator-based compaction scheme is introduced to provide higher compaction quality than existing approaches. The novel BIST scheme is generic, (i.e. independent of specific gate-level implementations of the multiplier cells and not requiring DFT in the multiplier) and thus it can be adopted by any module generator.