An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Effective Built-In Self-Test for Booth Multipliers
IEEE Design & Test
An Effective BIST Scheme for Arithmetic Logic Units
Proceedings of the IEEE International Test Conference
An Effective BIST Scheme for Ring-Address Type FIFOs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
Deterministic software-based self-testing of embedded processor cores
Proceedings of the conference on Design, automation and test in Europe
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Journal of Electronic Testing: Theory and Applications
Power-/Energy Efficient BIST Schemes for Processor Data Paths
IEEE Design & Test
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation
Journal of Systems Architecture: the EUROMICRO Journal
Easily Testable Cellular Carry Lookahead Adders
Journal of Electronic Testing: Theory and Applications
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Low Power BIST for Wallace Tree-Based Fast Multipliers
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
On Built-In Self-Test for Adders
Journal of Electronic Testing: Theory and Applications
Rapid, low-power loop execution in a network of functional units
Proceedings of the 17th Panhellenic Conference on Informatics
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