MIPS RISC architectures
An effective BIST architecture for fast multiplier cores
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
Instruction-Based Self-Testing of Processor Cores
Journal of Electronic Testing: Theory and Applications
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Realization-independent ATPG for designs with unimplemented blocks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Systematic software-based self-test for pipelined processors
Proceedings of the 43rd annual Design Automation Conference
Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Proceedings of the 20th annual conference on Integrated circuits and systems design
Software-based self-testing with multiple-level abstractions for soft processor cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid software-based self-testing methodology for embedded processor
Proceedings of the 2008 ACM symposium on Applied computing
Functional self-testing for bus-based symmetric multiprocessors
Proceedings of the conference on Design, automation and test in Europe
Processor Description Languages
Processor Description Languages
Functional processor-based testing of communication peripherals in systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
An evolutionary methodology for test generation for peripheral cores via dynamic FSM extraction
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Reducing the storage requirements of a test sequence by using a background vector
Proceedings of the Conference on Design, Automation and Test in Europe
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Software-Based Testing for System Peripherals
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new SBST algorithm for testing the register file of VLIW processors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 14.98 |
Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.