Software-based self test methodology for on-line testing of L1 caches in multithreaded multicore architectures

Authors:
Giorgos Theodorou;Nektarios Kranitis;Antonis Paschalis;Dimitris Gizopoulos
Affiliations:
Department of Informatics and Telecommunications, University of Athens, Athens, Greece;Department of Informatics and Telecommunications, University of Athens, Athens, Greece;Department of Informatics and Telecommunications, University of Athens, Athens, Greece;Department of Informatics and Telecommunications, University of Athens, Athens, Greece
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2013

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Abstract

The flexibility that allows the application of different March tests is a critical requirement for on-line testing of memory arrays. In a previous study, we have introduced a low-cost software-based self test (SBST) program development methodology for on-line periodic testing of L1 caches that utilizes direct cache access (DCA) instructions and exploits the native monitoring hardware available in modern architectures. In this brief, we discuss a multithreaded optimization of this SBST methodology that exploits the thread level parallelism of multithreaded multicore architectures in order to speed up March test execution by elaborating the low level multiple subbank cache organization. The effectiveness of the methodology and its multithreaded optimization is demonstrated on the L1 caches of OpenSPARC T1 processor. Our results showed a speedup of more than 1.7 when the multithreaded optimization is applied and an acceptable performance overhead (less than 11%), even in intensive periodic test scenarios.