Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Industrial evaluation of DRAM tests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Test Challenges in Nanometer Technologies
Journal of Electronic Testing: Theory and Applications
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
IEEE Transactions on Computers
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
ATS '00 Proceedings of the 9th Asian Test Symposium
March SS: A Test for All Static Simple RAM Faults
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
Experimental fault analysis of 1 Mb SRAM chips
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Realizing the Benefits of Structural Test for Intel Microprocessors
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Testing Static and Dynamic Faults in Random Access Memories
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Fault Primitive Based Analysis of Linked Faults in RAMs
MTDT '03 Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing
Defect-Oriented Dynamic Fault Models for Embedded-SRAMs
ETW '03 Proceedings of the 8th IEEE European Test Workshop
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Framework for Fault Analysis and Test Generation in DRAMs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Transition Tests for High Performance Microprocessors
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor
ITC '04 Proceedings of the International Test Conference on International Test Conference
Systematic Defects in Deep Sub-Micron Technologies
ITC '04 Proceedings of the International Test Conference on International Test Conference
An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"
IEEE Transactions on Computers
A March Test for Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transistors dedicated to such memories. This paper discusses the methodology used to develop effective and efficient cache tests, and the way it is implemented to optimize the test set used at Intel to test their 512-kB caches manufactured in a 0.13-µm technology. An example is shown where a maximal test set of 15 tests with a corresponding maximum test time of 160.942 ms/chip is optimized to only six tests that require a test time of only 30.498 ms/chip.