An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor

Authors:
David M. Wu;Mike Lin;Madhukar Reddy;Talal Jaber;Anil Sabbavarapu;Larry Thatcher
Affiliations:
Intel Corporation;Intel Corporation;Intel Corporation;Intel Corporation;Intel Corporation;Intel Corporation
Venue:
ITC '04 Proceedings of the International Test Conference on International Test Conference
Year:
2004

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Abstract

This paper describes an optimized DFT architecture and its implementation strategy for an Intel high performance (3 GHz) microprocessor. Major DFT features and ATPG techniques implemented are described and key results are presented to show the return-on-investments (ROI) in the high volumemanufacturing (HVM) test environments.